The present invention relates to a circuit, which uses an output transistor, for amplifying and outputting a pulse width modulated (PWM) signal corresponding to an input audio signal. More particularly, this invention relates to a circuit for amplifying and outputting audio signals capable of preventing the output transistor from being thermally destroyed due to an excessively large current due to an output short circuit in a BTL (Balanced Transformer-Less) output circuit such as a class D audio amplifier.
FIG. 16 shows a structure of a BTL output section of a conventional class D audio amplifier. FIG. 17 is a timing chart showing operation of the BTL output section. Referring to FIG. 16, a digital audio data D is audio pulse code modulated (PCM) data from a CD, an MD, a DVD, a BS or the like as a signal source. The number of bits and frequency of the data vary depending upon the signal source, but the number of bits is in a range of 14 to 24 bits, and the frequency is in a range of 1 to 4 fs=32 to 192 kHz (1 fs=32 to 48 kHz). For example, in the case of the CD, the number of bits is 16, and the frequency is 1 fs=44.1 kHz.
This digital audio data D is up-sampled by an over sampling digital filter 1, and modulated into 1 bit data strings IN1 and IN2 by a xcexa3xcex94 modulator circuit 2 and a PWM pulse generator circuit 3. In order to maintain the audio S/N precision, a period of the PWM pulse is selected in a range of about 1/(16 fs) to 1(64 fs), and the resolving power of the PWM pulse is selected in a range of about 1/(256 fs) to 1/(1024 fs) in many cases.
A signal level of each of the 1 bit data strings IN1 and IN2 output from the PWM pulse generator circuit 3 is about 3 to 5 V, the signal level is driven into about 20 to 50 V by a BTL output driver section 4, and output to LC filters 5a and 5b as amplified and output signals OUT1 and OUT2.
The 1 bit data string IN1 is input to a gate of an output transistor Tr11 as a positive phase input, and input to a gate of an output transistor Tr12 through an inverter I1 as a negative phase input, and output as the amplified and output signal OUT1. Similarly, the 1 bit data string IN2 is input to a gate of an output transistor Tr21 as a positive phase input, and input to a gate of an output transistor Tr22 through an inverter 12 as a negative phase input, and output as the amplified output signal OUT2.
As shown in FIG. 17, in the BTL output, an ON time period xe2x80x9caxe2x80x9d of a PWM pulse cycle of the 1 bit data string IN1 and an OFF time period xe2x80x9cbxe2x80x9d of a PWM pulse cycle of the 1 bit data string IN2 are the same. That is, the data strings IN1 and IN2 have opposite phases, i.e., so-called BTL outputs.
In order to enhance the electric power converting efficiency, it is necessary to reduce the ON resistances of the output transistors Tr11, Tr12, Tr21 and Tr22 which amplify and output the amplified and output signals OUT1 and OUT2. In a normal audio amplifier, the ON resistance is set to 0.3 xcexa9 or less.
The amplified and output signals OUT1 and OUT2 are output to a speaker 10 as analogue signals in which PWM signals represented by the amplified and output signals OUT1 and OUT2 are smoothed through the LC filters 5a and 5b, respectively.
The above-described BTL output section does not have a protection circuit that protects the output from a short circuit. In addition, the speaker 10 has two speaker terminals T1 and T2 which are positive terminals. Therefore, there is a problem in that in the BTL output, an excessively large current may flow at the time of an output short circuit, and the output transistors Tr11, Tr12, Tr21 and Tr22 are then destroyed.
For example, there is an adverse possibility that a user erroneously brings a connection wire into contact with a chassis of the BTL output section or the speaker terminals T1 and T2 are short circuited when the wire of the speaker 10 is connected. In that case, if the speaker terminal T1 is short-circuited with the chassis, i.e., ground (GND), the excessively great current flows when the output transistor Tr11 closer to the power source is ON, and the output transistor Tr11 is destroyed by heat.
Therefore, in some conventional protection circuits, a resistance is inserted in series with the output transistor, an excessively large current is detected from a potential difference between opposite ends of this resistor, and if an excessively large current is detected, the output transistor is turned OFF. However, this protection circuit cannot be applied to the class D amplifier that needs a reduced output resistance.
It is an object of this invention to provided a circuit for amplifying and outputting audio signals capable of preventing the output transistor from being thermally destroyed due to excessively large current caused by output short circuit in a class D audio amplifier.
The circuit for amplifying and outputting audio signals according to this invention comprises a comparing unit which compares a detection voltage and a predetermined voltage to output a stop signal, and when the detection voltage exceeded the predetermined voltage, outputs a stop signal. The detection voltage here is a potential difference between a source and a drain of the output transistor. The circuit further comprises, a transistor protection control unit which controls to turn OFF an output of the output transistor when the comparing unit output the stop signal.
According to the invention, the comparing unit compares the detection voltage and the predetermined voltage. When the detection voltage exceeded the predetermined voltage, a stop signal is output. When the stop signal is output, the output of the output transistor is turned OFF. Accordingly, flow of excessively large current to the output transistor due to the short circuit of the output can be prevented.
The circuit for amplifying and outputting audio signals may further preferably comprise many output transistors. In such a case, each output transistor is provided with the comparing unit and the transistor protection control unit.
Furthermore, all of the output transistors are turned OFF when the stop signal is output.
Furthermore, it is preferable that the transistor protection control unit comprises a latch circuit which latches the stop signal using the PWM signal as a clock signal, and an AND circuit provided on a gate input side of the output transistor which calculates a logical multiplication of the PWM signal and an inverted signal of the stop signal, and turns the output transistor OFF irrespective of the PWM signal.
Furthermore, it is preferable that the comparing unit comprises a square/divide circuit which outputs a judgment current value obtained by dividing a square value of a detection current value corresponding to the detection voltage and a first bias current value by a second bias current value; and a judging circuit which outputs the stop signal when the judgment current value exceeded a third bias current value.
Furthermore, it is preferable that the circuit for amplifying and outputting audio signals further comprises a first counting unit which counts the number of outputs of the stop signal output from the comparing unit using the PWM as a clock signal, and outputs the stop signal to the transistor protection control unit when the number of output exceeded a first predetermined value, and a second counting unit which counts a clock signal using the PWM signal as the clock signal, and which resets the counting by the second counting unit when the counted number value exceeded a second predetermined value which is greater than the first predetermined value.
Furthermore, it is preferable that the circuit for amplifying and outputting audio signals further comprises a clock generator circuit which generates a clock and outputs the same as a clock signal of the first counting unit and the second counting unit when a pulse width of the PWM signal is equal to or greater than a predetermined width based on the PWM signal and a logical multiplication signal which is a logical multiplication of the PWM signal and a delayed PWM signal which is obtained by delaying the PWM signal, a clock is generated when a pulse width of the PWM signal is equal to or greater than a predetermined width.
Furthermore, it is preferable that the clock generator circuit includes a delay circuit which delays the PWM signal by a gate delay.
Furthermore, it is preferable that the clock generator circuit includes a self-induction oscillator circuit which generates a self-induction oscillated clock, and a shift resistor which delays the PWM signal using the self-induction oscillated clock.
Furthermore, it is preferable that the circuit for amplifying and outputting audio signals further comprises a third counting unit which counts the self-induction oscillated clock or an independent self-induction oscillated clock when the stop signal is output from the comparing unit. The third counting unit outputs the stop signal output to the transistor protection control unit when the counted value exceeded a third predetermined value.
Furthermore, it is preferable that the latch circuit, the second counting unit and the third counting unit reset the latch processing or the counting processing by the release signal input from outside.
Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.